Geoff is no longer with the SPM group - This page is kept for archival purposes,
but more recent info is found at http://research.geoffknagge.com

Projects

The following lists some of the projects that I have worked on while with the SPM group.

Model Predictive Control

This project is concerned with development of algorithms and hardware for high-speed model predictive control (MPC) solutions. Both linear and nonlinear MPC systems are considered.

Sub-Projects

c4Hardware - limited precision modelling in C++

c4Hardware is a highly flexible library of C++ classes (available for free download) for the emulation of hardware implementations of algorithms. It provides a high level interface to matrix, vector, and scalar operations to allow rapid application development without requiring knowledge of the underlying operations. Futhermore, it allows custom data types to be plugged-in with little change to the high level application. This allows bit-accurate modelling and analysis of algorithms under various limited precision numerical representations.
Team Members: Dr. Geoff Knagge

Sub-Projects

Sphere (lattice) detection and Tree Search Algorithms in Hardware

This project investigates the use of the sphere detection methods as a form of lattice detection, to provide near maximum likelihood results to combinatorial optimisation problems. This important problem has many applications, such as multi-user detection and MIMO detection, in wireless communications. The main focus of this project concerns practicality of lattice detection algorithms in hardware, particularly for higher order search spaces.
Team Members: Dr. Geoff Knagge

Sub-Projects

c4HDL - C++ for bit-accurate modelling of HDL

c4HDL is a library of C++ classes (available for free download) that provides bit-accurate modelling of integer, floating point, and fixed point data types, for matching with HDL code. Key points include :
  • Allows modelling from very small to very large numerical precision
  • Models can be directly used for generating testbench data to verify the operation of HDL models of the algorithm.
  • Contains and generates matching C++ and VHDL models of some arithmetic hardware components
While designed as a plug-in for c4Hardware, this library may also be used as a standalone item.
Team Members: Dr. Geoff Knagge

Algorithms to ASICs

These projects are focussed on providing software solutions to assist the mapping of algorithmic solutions to actual implementations in hardware devices. This includes bit accurate modelling of numerical systems in limited precision, analysis of those simulations, and generation of test data for verification with hardware implementations in ASICs and FPGAs.

Sub-Projects

MIMO Communications Testbed

This is a hardware device designed to be used in the design and testing of wireless MIMO communications systems. It is connected to a PC via USB 2.0 or ethernet and uses an on-board FPGA to allow implementation of algorithms in logic, together with provision for multiple radio modules.