MIMO Communications Testbed


The custom built MIMO Communications testbed is based on a main baseband board capable of controlling up to 4 RF boards. Combining two of these complete systems provides capability for any MIMO antenna configuration scenario up to 4x4. The digital board provides an interface to a host PC via USB or Ethernet connection, and an FPGA to process baseband signals to ADC's and from DACs on the radio modules. The baseband design is centered around an Altera Stratix II FPGA.

Block Diagram of Testbed

The FPGA Advantage

A challenge in traditional MIMO testbed design is the amount of data that must be transferred between the baseband and radios. For example, using 4 receivers with 14-bit ADC's at 40MHz sampling rates requires a transfer rate of 4.48Gbps. By using FPGA at the core of the design, the testbed is able leverage the high I/O capability on PLD's and achieve the high data tranfer rates. To allow the capture of long frame lengths, additional storage is provided to the FPGA using an external static random access memory (SRAM). This memory can store 144Mbits of I/Q data, which is equivalent to a transmission block length of 15.7ms using 12 bit I/Q data. This frame length is adequate for testing short burst transmissions.

External Interfacing

A common support bus provides host interface connections via USB 2 or Ethernet as well as Flash memory and program memory for the Nios II processor core running on the FPGA. The FPGA is the main processing component, under the control of a Nios II core. This core runs custom software that provides access to and from the host PC to control the testbed. The core interprets host commands and configures the radio modules via control registers.

Once the testbed is configured, the host can then begin a test by starting the signal processing block on the FPGA. In the simplest configuration, this block will simply send I/Q data from the host to the transmitters and capture received signals for offline processing by the host. In more complicated scenarios the user can implement algorithms to process baseband signals in a realtime environment on the FPGA.


Additional computational power can be added via a high speed 32-bit bus. The testbed has been designed to enable the direct connection of a Texas Instruments DSP development kit via the Universal Host-Port Interface (UHPI). This bus can also be used to interface to custom ASICs to provide a versatile testing environment. Multiple baseband boards may also be combined to generate MIMO test systems with higher than 4x4 capability through common clocking schemes and a small number of control signals.

Radio Modules

The radio frequency (RF) modules developed use the 2.4GHz to 2.5GHz ISM band, and provide a transmission bandwidth up to 40MHz via the Maxim MAX2829 transceiver chip. These implement a direct conversion process, removing the need for IF stage design. Moreover, the MAX2829 chips are designed for use in MIMO applications, with a mode to enable clock synchronisation between multiple transceiver chips.

Additionally, a power amplifier and T/R switch are incorporated. Each RF board contains I/Q ADC and DAC's capable of 12 or 14 bit operation and connect directly to the baseband board FPGA. The ADC can be operated at up to 80Msps whilst the DACs are rated at 500MHz, allowing more flexibility for pulse shaping. All RF boards use a common 40MHz clock generated on the baseband board that can be adjusted using firmware to provide frequency offset corrections. The ADC/DAC can run off the same clock as the transceivers, or a user defined clock by configuring the FPGA PLLs. An external clock source may also be used via a SMA connector if desired. Most configurable options for the RF module components are carried out through serial interfaces, with some direct I/O connections from the FPGA.

Maintained by Prof. Brett Ninness
University of Newcastle
7 May 2008, © Copyright