This project has implemented a Low Density Parity Check (LDPC) decoder in field programmable gate array (FPGA) hardware. The key design feature of the decoder is flexibility, being able to support different codes and rates. The advantages of being able to test a variety of codes such as those found in communications standards including Wireless LAN (IEEE 802.lln), WIMAX (IEEE 801.16e) and DVB-S2, on a single hardware platform will make the transition from theory to practice a much smoother one. The LDPC decoder designed is flexible, it can accept a new code without any redesign, the only thing that changes is the ROM configuration. It has been tested via its serial Matlab interface and has been functionally verified, performing to within 1dB of a Matlab floating point testbench. The decoder has also been shown to operate correctly on large codes and as performance demands increase, it has been shown to scale up to larger designs well.