Dr Vikram A. Chandrasetty
Phone+61 (02) 492 15385
Fax+61 (02) 492 16993
PostDr Vikram A. Chandrasetty
Currently in Bangalore, India
Faculty of Built Engineering and Built Environment,
The University of Newcastle,
Callaghan, NSW 2308,
Vikram Arkalgud Chandrasetty received Bachelor Degree in Electronics and Communication Engineering from Bangalore University (India) in 2004, Master Degree in VLSI System Design from Coventry University (UK) in 2008 and PhD in Computer Systems Engineering from University of South Australia (Australia) in 2012.
He was working with Core Networks Division at Motorola as Software Engineer (2005–2007), where he was part of the billing and call processing R&D team. He also worked for SoftJin Technologies as Senior Software Engineer (2007–2008) focusing on Electronic Design Automation (EDA) and FPGA application design. He was involved in the design and development of Programmable Synthesis Engine (PSE) for custom FPGA architectures and structured ASICs. He was also working on software modeling and FPGA implementation of Motion Estimation algorithms for H.264 Advance Video Coder.
Dr Vikram was researching on low complexity algorithms for decoding Low-Density Parity-Check (LDPC) codes and investigating efficient architectures for hardware implementation for his PhD. His research was mainly focused on implementing high performance LDPC decoders on reconfigurable devices.
He worked as a Postdoctoral Research Fellow at the University of Newcastle with the SPM group. His research was mainly focused on design and implementation of Spatially-coupled LDPC codes in hardware.
Personal website: www.vikramac.com
Some current projects:
These projects are focussed on providing software solutions to assist the mapping of algorithmic solutions to actual implementations in hardware devices. This includes bit accurate modelling of numerical systems in limited precision, analysis of those simulations, and generation of test data for verification with hardware implementations in ASICs and FPGAs.
This project investigates the design and decoding of low-density parity-check (LDPC) codes and a related class of codes called repeat- accumulate (RA) codes. This project includes an online implementation of density evolution and offers resources related to LDPC and RA codes.